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Works (8)

A gem5 trace-driven simulator for fast architecture exploration of OpenMP workloads

Microprocessors and Microsystems
2019-06 | Journal article
Contributors: Alejandro Nocua; Florent Bruguier; Gilles Sassatelli; Abdoulaye Gamatié
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Crossref

A Cross-Level Power Estimation Technique to Enhance High-Level Power Models Quality

J. Low Power Electronics
2017 | Journal article
Source: Self-asserted source
Alejandro Nocua Cifuentes

HPET: An Efficient Hybrid Power Estimation Technique to Improve High-Level Power Characterization

Journal of Circuits, Systems, and Computers
2017 | Journal article
Source: Self-asserted source
Alejandro Nocua Cifuentes
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2016 IEEE 19th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS), Kosice, Slovakia, April 20-22, 2016

2016 | Conference paper
Part of ISBN: 978-1-5090-2467-4
Source: Self-asserted source
Alejandro Nocua Cifuentes

2016 IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2016, Tallinn, Estonia, September 26-28, 2016

2016 | Conference paper
Part of ISBN: 978-1-5090-3561-8
Source: Self-asserted source
Alejandro Nocua Cifuentes

A Hybrid Power Estimation Technique to improve IP power models quality

2016 IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2016, Tallinn, Estonia, September 26-28, 2016
2016 | Conference paper
Source: Self-asserted source
Alejandro Nocua Cifuentes

A hybrid power modeling approach to enhance high-level power models

2016 IEEE 19th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS), Kosice, Slovakia, April 20-22, 2016
2016 | Conference paper
Source: Self-asserted source
Alejandro Nocua Cifuentes

Screening small-delay defects using inter-path correlation to reduce reliability risk

Microelectronics Reliability
2015 | Journal article
Source: Self-asserted source
Alejandro Nocua Cifuentes