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A 103 fJ/b/dB, 10–26 Gb/s Receiver With a Dual Feedback Nested Loop CDR for Wide Bandwidth Jitter Tolerance Enhancement

IEEE Journal of Solid-State Circuits
2023 | Journal article
Contributors: Yao-Chia Liu; Wei-Zen Chen; Yuan-Sheng Lee; Yu-Hsiang Chen; Shawn Ming; Ying-Hsi Lin
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A 25-Gb/s, 2.1-pJ/bit, Fully Integrated Optical Receiver With a Baud-Rate Clock and Data Recovery

IEEE Journal of Solid-State Circuits
2019-08 | Journal article
Contributors: Yuan-Sheng Lee; Wei-Hsiang Ho; Wei-Zen Chen
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