Personal information

Other IDs

ResearcherID: K-8257-2018

Keywords

Analog VLSI, Analog Circuit Design and Automation, Metaheuristic Algorithms, Optimization

Countries

India

Activities

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Education and qualifications (3)

National Institute of Technology Warangal: Warangal, Telangana, IN

2016-01-08 to present | Doctor of Philosophy (Electronics and Communication Engineering)
Education
Source: Self-asserted source
M A Mushahhid Majeed

Osmania University: Hyderabad, Telangana, IN

2013-07-14 to 2015-07-10 | Master of Engineering (Electronics and Communication Engineering)
Education
Source: Self-asserted source
M A Mushahhid Majeed

Osmania University: Hyderabad, Telangana, IN

2009-06-13 to 2013-06-16 | Bachelor of Engineering (Electronics and Communication Engineering)
Education
Source: Self-asserted source
M A Mushahhid Majeed

Works (9)

Optimal Design of CMOS Analog Circuit Using Enhanced Grey Wolf Optimization Algorithm

Journal of Advanced Research in Dynamical and Control Systems
2018 | Journal article
Source: Self-asserted source
M A Mushahhid Majeed

Optimal Design of CMOS Amplifier Circuits Using Whale Optimization Algorithm

Communications in Computer and Information Science
2018-10-10 | Book chapter
Part of ISBN: 978-981-13-2372-0
Source: Self-asserted source
M A Mushahhid Majeed

An enhanced grey wolf optimization algorithm with improved exploration ability for analog circuit design automation

TURKISH JOURNAL OF ELECTRICAL ENGINEERING & COMPUTER SCIENCES
2018-09-28 | Journal article
DOI: 10.3906/elk-1802-110
Contributors: MA Mushahhid MAJEED; Sreehari Rao PATRI
Source: check_circle
Crossref

Influence of Thickness of Oxide and Dielectric Constant on Short Channel Metrics in FinFETs

Journal of Advanced Research in Dynamical and Control Systems
2017 | Journal article
Source: Self-asserted source
M A Mushahhid Majeed

Optimization of CMOS Analog Circuits Using Grey Wolf Optimization Algorithm

2017 14th IEEE India Council International Conference (INDICON)
2017 | Conference paper
DOI: 10.1109/INDICON.2017.8487592
Source: Self-asserted source
M A Mushahhid Majeed

Optimization of CMOS analog circuits using sine cosine algorithm

2017 8th International Conference on Computing, Communication and Networking Technologies (ICCCNT)
2017 | Conference paper
DOI: 10.1109/ICCCNT.2017.8204048
Source: Self-asserted source
M A Mushahhid Majeed

A design of 2nd order DT sigma-delta modulator for medical implants

2015 IEEE Asia Pacific Conference on Postgraduate Research in Microelectronics and Electronics (PrimeAsia)
2015 | Conference paper
DOI: 10.1109/PrimeAsia.2015.7450460
Source: Self-asserted source
M A Mushahhid Majeed

Design of two-stage Load Compensated OTA for Sigma-Delta ADC in Medical Implants

National Conference on Circuits, Signals and Systems (NCCSS 2015)
2015 | Conference paper
Source: Self-asserted source
M A Mushahhid Majeed

Polyphase Decomposition of Comb Decimation Filter for single-bit Sigma-Delta Analog to Digital Converters

44th Mid-Term Symposium on �ICT in Space, Defense and Industrial Applications�
2013 | Conference paper
Source: Self-asserted source
M A Mushahhid Majeed
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