Personal information

Other IDs

Scopus Author ID: 24558806300

Activities

Collapse all

Employment (1)

Dongwoon Anatech: Seoul, Seocho-gu, KR

2021-05-01 to present | Principal Research Engineer (RnD)
Employment
Source: Self-asserted source
Jeongseok chae

Education and qualifications (1)

Oregon State University: Corvallis, OR, US

2006-09 to 2011-03 | PhD (EECS)
Education
Source: Self-asserted source
Jeongseok chae

Works (17)

Study on switch-leakage-induced dark offset of ambient light sensor

Electronics Letters
2019-03-21 | Journal article
DOI: 10.1049/el.2018.5547
Part of ISSN: 0013-5194
Part of ISSN: 1350-911X
Source: Self-asserted source
Jeongseok chae
grade
Preferred source (of 3)‎

A 12-Bit 7 mu W/Channel 1 kHz/Channel Incremental ADC for Biosensor Interface Circuits

IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS), VOLS 1-6, CONFERENCE PROCEEDINGS
2012 | Journal article
WOSUID: WOS:000316903703042
Contributors: Chen, Chia-Hung; Crop, Joseph; Chae, Jeongseok; Chiang, Patrick; Temes, Gabor C.
Source: check_circle
Web of Science Researcher Profile Sync

A 12-bit 7 µW/channel 1 kHz/channel incremental ADC for biosensor interface circuits

2012 IEEE International Symposium on Circuits and Systems
2012-05 | Conference paper
DOI: 10.1109/iscas.2012.6271940
ISBN: 9781467302197
ISBN: 9781467302180
ISBN: 9781467302173
Source: Self-asserted source
Jeongseok chae
grade
Preferred source (of 2)‎

A Double-Sampled Low-Distortion Cascade Delta Sigma Modulator with an Adder/Integrator for WLAN Application

IEEE Custom Integrated Circuits Conference (CICC)
2011 | Conference paper
WOSUID: WOS:000296981700009
Source: check_circle
Web of Science Researcher Profile Sync

A double-sampled low-distortion cascade ΔΣ modulator with an adder/integrator for WLAN application

Proceedings of the Custom Integrated Circuits Conference
2011 | Conference paper
DOI: 10.1109/CICC.2011.6055289
EID:

2-s2.0-80455156142

ISBN: 9781457702228
Part of ISSN: 08865930
Contributors: Lee, S.; Chae, J.; Aniya, M.; Takeuchi, S.; Hamashita, K.; Hanumolu, P.K.; Temes, G.C.
Source: Self-asserted source
Jeongseok chae via Scopus - Elsevier

Low-power and low-offset comparator using latch load

Electronics Letters
2011 | Journal article
DOI: 10.1049/el.2010.3070
Part of ISSN: 0013-5194
Source: Self-asserted source
Jeongseok chae
grade
Preferred source (of 3)‎

A 63 dB 16 mW 20 MHz BW Double-Sampled Delta Sigma Analog-to-Digital Converter with an Embedded-Adder Quantizer

IEEE Custom Integrated Circuits Conference
2010 | Conference paper
WOSUID: WOS:000287027300105
Source: check_circle
Web of Science Researcher Profile Sync

A 63 dB 16 mW 20 MHz BW double-sampled ΔΣ analog-to-digital converter with an embedded-adder quantizer

Proceedings of the Custom Integrated Circuits Conference
2010 | Conference paper
DOI: 10.1109/CICC.2010.5617594
EID:

2-s2.0-78649816071

ISBN: 9781424457588
Part of ISSN: 08865930
Contributors: Chae, J.; Lee, S.; Aniya, M.; Takeuchi, S.; Hamashita, K.; Hanumolu, P.K.; Temes, G.C.
Source: Self-asserted source
Jeongseok chae via Scopus - Elsevier

Comparator-based buffer with resistive error correction

Electronics Letters
2010 | Journal article
DOI: 10.1049/el.2010.0521
Part of ISSN: 0013-5194
Source: Self-asserted source
Jeongseok chae
grade
Preferred source (of 3)‎

A Noise-Coupled Time-Interleaved Delta-Sigma ADC With 4.2 MHz Bandwidth,-98 dB THD, and 79 dB SNDR

IEEE Journal of Solid-State Circuits
2008 | Journal article
DOI: 10.1109/JSSC.2008.2006311
WOSUID: WOS:000261801800003
Source: check_circle
Web of Science Researcher Profile Sync
grade
Preferred source (of 2)‎

A Noise-Coupled Time-Interleaved ¿¿ ADC with 4.2MHz BW, -98dB THD, and 79dB SNDR

IEEE International Solid-State Circuits Conference (ISSCC)
2008 | Conference paper
DOI: 10.1109/ISSCC.2008.4523273
Contributors: Kyehyung Lee; Jeongseok Chae; Mitsuru Aniya; Koichi Hamashita; Kaoru Takasuka; Seiji Takeuchi; Gabor C. Temes
Source: check_circle
Web of Science Researcher Profile Sync
grade
Preferred source (of 2)‎

Efficient fully-floating double-sampling integrator for Delta Sigma ADCs

IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS), VOLS 1-6, CONFERENCE PROCEEDINGS
2008 | Journal article
DOI: 10.1109/ISCAS.2008.4541699
WOSUID: WOS:000258532101091
Contributors: Lee, Kyehyung; Chae, Jeongseok; Temes, Gabor C.
Source: check_circle
Web of Science Researcher Profile Sync
grade
Preferred source (of 2)‎

Efficient floating double-sampling integrator for ADCs

Electronics Letters
2007 | Journal article
DOI: 10.1049/el:20072769
Part of ISSN: 0013-5194
Source: Self-asserted source
Jeongseok chae
grade
Preferred source (of 3)‎

Output-buffer-delay modeling circuit for a high-speed data interface

Journal of the Korean Physical Society
2002 | Journal article
DOI: 10.3938/JKPS.40.709
WOSUID: WOS:000175022300035
Contributors: Park, YJ; Chae, JS; Kim, DM; Kim, D
Source: check_circle
Web of Science Researcher Profile Sync
grade
Preferred source (of 2)‎

Picosecond load-adaptive output-buffer-delay modeling circuit for a hierarchical delay-locked loop

Journal of the Korean Physical Society
2002 | Journal article
WOSUID: WOS:000179871300002
Contributors: Kim, SH; Chae, JS; Kim, D; Kim, DM
Source: check_circle
Web of Science Researcher Profile Sync

Picosecond load-adaptive output-buffer-delay modeling circuit for a hierarchical delay-locked loop

Journal of the Korean Physical Society
2002 | Conference paper
EID:

2-s2.0-0036946517

Part of ISSN: 03744884
Contributors: Kim, S.H.; Chae, J.S.; Kim, D.; Kim, D.M.
Source: Self-asserted source
Jeongseok chae via Scopus - Elsevier

Wide range single-way-pumping synchronous mirror delay

Electronics Letters
2000 | Journal article
DOI: 10.1049/el:20000711
Part of ISSN: 0013-5194
Source: Self-asserted source
Jeongseok chae
grade
Preferred source (of 3)‎

Peer review (10 reviews for 1 publication/grant)

Review activity for Electronics letters. (10)
How many people are using ORCID?