Personal information

India, Spain

Biography

Mohit D. Ganeriwala is a Marie Skłodowska-Curie Actions (MSCA) postdoctoral researcher at the Department of Electronics and Computer Technology at the University of Granada.
He has active research experience and interests in the area of slid-state device physics, RRAM/memristors, nano-scale device modeling and characterisation.

He received BTech (2012) (Gold medal for academic excellence) in Electronics and Communications from Nirma University India, MTech (2015) (Gold medal for academic excellence and Best research award) and PhD (2020) in Electrical Engineering from the Indian Institute of Technology (IIT) Gandhinagar, India

From May 2020 to Jan 2022 he worked on the post of principal engineer, Compact modeling and characterization at GlobalFoundries. His PhD was focused on developing computationally efficient compact models for III-V Mutli-Gate transistors. He has been a visiting researcher at different National and international institutions including ISRO, India (2012), IIT Kanpur (2015) and JAIST, Japan (2016). And has authored several scientific contributions in various peer-reviewed Journals and International conference proceedings, being an active reviewer of articles from international journals and conferences. He has received several grants and fellowships such as MSCA-IF, European Commission (2021), Visvesvaraya PhD Fellowship, MeitY, Government of India (2015), JASSO Internship Grant, Japan (2016).

Apart from research, he was actively involved in teaching various courses (Semiconductor device modeling, Physics of transistors etc.) and has also received an outstanding graduate teaching fellow award for the same.

Activities

Education and qualifications (2)

Indian Institute of Technology Gandhinagar: Gandhinagar, Gujarat, IN

2015-06-10 to 2020-08 | PhD (Electrical Engineering)
Education
Source: Self-asserted source
Mohit D. Ganeriwala

Indian Institute of Technology Gandhinagar: Gandhinagar, Gujarat, IN

2013 to 2015 | MTech (Electrical Engineering)
Education
Source: Self-asserted source
Mohit D. Ganeriwala

Works (24)

A Scalable Physics-Based Compact Model for Terminal Charge, Intrinsic Capacitance and Drain Current in Nanosheet Field Effect Transistors

IEEE Journal of the Electron Devices Society
2025 | Journal article
Contributors: Aishwarya Singh; Mohit D. Ganeriwala; Radhika Joglekar; Nihar R. Mohapatra
Source: check_circle
Crossref

Volatile MoS2 Memristors with Lateral Silver Ion Migration for Artificial Neuron Applications

Small Science
2025-01-27 | Journal article
Contributors: Sofía Cruces; Mohit Dineshkumar Ganeriwala; Jimin Lee; Lukas Völkel; Dennis Braun; Annika Grundmann; Ke Ran; Enrique González Marín; Holger Kalisch; Michael Heuken et al.
Source: check_circle
Crossref

TCAD-based investigation of 1/f noise in advanced 22 nm FDSOI MOSFETs

Applied Physics Letters
2024-11-11 | Journal article
Contributors: Prabhat Khedgarkar; Mohit D. Ganeriwala; Pardeep Duhan
Source: check_circle
Crossref

Role of Point Defects and Ion Intercalation in Two-Dimensional Multilayer Transition Metal Dichalcogenide Memristors

ACS Applied Nano Materials
2024-11-08 | Journal article
Contributors: Mohit D. Ganeriwala; Alejandro Toral-López; Estela Calaforra-Ayuso; Francisco Pasadas; Francisco G. Ruiz; Enrique G. Marin; Andres Godoy
Source: check_circle
Crossref

Numerical study of synaptic behavior in amorphous HfO2-based ferroelectric-like FETs generated by voltage-driven ion migration

Journal of Applied Physics
2024-09-28 | Journal article
Contributors: J. Cuesta-Lopez; M. D. Ganeriwala; E. G. Marin; A. Toral-Lopez; F. Pasadas; F. G. Ruiz; A. Godoy
Source: check_circle
Crossref

A Flexible Laser-Induced Graphene Memristor with Volatile Switching for Neuromorphic Applications

ACS Applied Materials & Interfaces
2024-09-18 | Journal article
Contributors: Mohit D. Ganeriwala; Roberto Motos Espada; Enrique G. Marin; Juan Cuesta-Lopez; Mikel Garcia-Palomo; Noel Rodríguez; Francisco G. Ruiz; Andres Godoy
Source: check_circle
Crossref

Reconfigurable frequency multipliers based on graphene field-effect transistors

Discover Nano
2023-10-05 | Journal article
Part of ISSN: 2731-9229
Contributors: A. Toral-Lopez; E. G. Marin; F. Pasadas; M. D. Ganeriwala; F. G. Ruiz; D. Jiménez; A. Godoy
Source: Self-asserted source
Mohit D. Ganeriwala

A simplified approach to include confinement induced band structure changes into the NsFET compact model

2022 IEEE International Conference on Emerging Electronics (ICEE)
2022-12-11 | Conference paper
Contributors: Aishwarya Singh; Mohit D. Ganeriwala; Ramandeep Kaur; Nihar R. Mohapatra
Source: Self-asserted source
Mohit D. Ganeriwala

A Bottom-Up Scalable Compact Model for Quantum Confined Nanosheet FETs

IEEE Transactions on Electron Devices
2022-01 | Journal article
Contributors: Mohit D. Ganeriwala; Aishwarya Singh; Abhilash Dubey; Ramandeep Kaur; Nihar R. Mohapatra
Source: check_circle
Crossref
grade
Preferred source (of 2)‎

A unified compact model for electrostatics of III–V GAA transistors with different geometries

Journal of Computational Electronics
2021-10-07 | Journal article
Contributors: Mohit D. Ganeriwala; Francisco G. Ruiz; Enrique G. Marin; Nihar R. Mohapatra
Source: check_circle
Crossref
grade
Preferred source (of 2)‎

Insights into the Mechanical and Electrical Properties of a Metal–Phosphorene Interface: An Ab Initio Study with a Wide Range of Metals

ACS Omega
2021-03-23 | Journal article
Part of ISSN: 2470-1343
Part of ISSN: 2470-1343
Source: Self-asserted source
Mohit D. Ganeriwala
grade
Preferred source (of 2)‎

Significance of L-valley charges and a method to include it in electrostatic model of III-V GAA FETs

2020 4th IEEE Electron Devices Technology & Manufacturing Conference (EDTM)
2020-04 | Conference paper
Source: Self-asserted source
Mohit D. Ganeriwala
grade
Preferred source (of 2)‎

A compact model for III–V nanowire electrostatics including band non-parabolicity

Journal of Computational Electronics
2019-12-13 | Journal article
Contributors: Mohit D. Ganeriwala; Francisco G. Ruiz; Enrique G. Marin; Nihar R. Mohapatra
Source: check_circle
Crossref
grade
Preferred source (of 2)‎

Capacitance and Surface Potential Model for III-V Double-Gate FET

2019 2nd International Symposium on Devices, Circuits and Systems (ISDCS)
2019-03 | Conference paper
Source: Self-asserted source
Mohit D. Ganeriwala
grade
Preferred source (of 2)‎

Charge and Capacitance Compact Model for III-V Quadruple-Gate FETs With Square Geometry

2019 IEEE Conference on Modeling of Systems Circuits and Devices (MOS-AK India)
2019-02 | Conference paper
Source: Self-asserted source
Mohit D. Ganeriwala
grade
Preferred source (of 2)‎

A Compact Charge and Surface Potential Model for III–V Cylindrical Nanowire Transistors

IEEE Transactions on Electron Devices
2019-01 | Journal article
Contributors: Mohit D. Ganeriwala; Francisco G. Ruiz; Enrique G. Marin; Nihar R. Mohapatra
Source: check_circle
Crossref
grade
Preferred source (of 2)‎

An Unified Charge Centroid Model for Silicon and Low Effective Mass III-V Channel Double Gate MOS Transistors

2019 32nd International Conference on VLSI Design and 2019 18th International Conference on Embedded Systems (VLSID)
2019-01 | Conference paper
Source: Self-asserted source
Mohit D. Ganeriwala
grade
Preferred source (of 2)‎

A Simple Charge and Capacitance Compact Model for Asymmetric III-V DGFETs Using CCDA

2018 4th IEEE International Conference on Emerging Electronics (ICEE)
2018-12 | Conference paper
Source: Self-asserted source
Mohit D. Ganeriwala
grade
Preferred source (of 2)‎

Computationally efficient analytic charge model for III-V cylindrical nanowire transistors

2018 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon (EUROSOI-ULIS)
2018-03 | Conference paper
Source: Self-asserted source
Mohit D. Ganeriwala
grade
Preferred source (of 2)‎

Modeling of Quantum Confinement and Capacitance in III–V Gate-All-Around 1-D Transistors

IEEE Transactions on Electron Devices
2017-12 | Journal article
Part of ISSN: 0018-9383
Part of ISSN: 1557-9646
Source: Self-asserted source
Mohit D. Ganeriwala
grade
Preferred source (of 3)‎

Compact Modeling of Gate Capacitance in III–V Channel Quadruple-Gate FETs

IEEE Transactions on Nanotechnology
2017-07 | Journal article
Part of ISSN: 1536-125X
Part of ISSN: 1941-0085
Source: Self-asserted source
Mohit D. Ganeriwala
grade
Preferred source (of 2)‎

Modeling of Charge and Quantum Capacitance in Low Effective Mass III-V FinFETs

IEEE Journal of the Electron Devices Society
2016-11 | Journal article
Part of ISSN: 2168-6734
Source: Self-asserted source
Mohit D. Ganeriwala
grade
Preferred source (of 2)‎

Effect of Pregate Carbon Implant on Narrow Width Behavior and Performance of High- Metal-Gate nMOS Transistors

IEEE Transactions on Electron Devices
2016-07 | Journal article
Part of ISSN: 0018-9383
Part of ISSN: 1557-9646
Source: Self-asserted source
Mohit D. Ganeriwala
grade
Preferred source (of 2)‎

Anomalous Width Dependence of Gate Current in High-K Metal Gate nMOS Transistors

IEEE Electron Device Letters
2015-08 | Journal article
Part of ISSN: 0741-3106
Part of ISSN: 1558-0563
Source: Self-asserted source
Mohit D. Ganeriwala
grade
Preferred source (of 2)‎

Peer review (1 review for 1 publication/grant)

Review activity for Nano letters. (1)